A 3.6-μW sub-lV fast-transient-response output-capacitor-free LDO regulator in 0.13-μm CMOS technology

Author

Xi Qu ; Ze-kun Zhou ; Xin Ming ; Bo Zhang

Author_Institution

State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

A sub-1V output capacitor-free CMOS low-dropout regulator, which can realize fast transient behavior with low power dissipation, is presented in this paper. The proposed LDO regulator utilizes class AB operational amplifier to increase the slew rate at the gate of power PMOS transistor during transient state. An extra slew rate enhancement circuit is adopted to deliver extra current when the output voltage increases suddenly with automatic shut-off property. The proposed LDO regulator has been designed and simulated in a standard 0.13-μm CMOS process. The LDO regulator can deliver 100mA load current at 0.9V input voltage with 200mV dropout voltage. The output voltage is able to recover within 1.6μs at 4 μA quiescent current, when the output current steps from 50μA to 100mA.

Keywords

CMOS analogue integrated circuits; capacitors; CMOS technology; current 50 A to 100 mA; extra slew rate enhancement circuit; output; power 3.6 W; power PMOS transistor; power dissipation; size 0.13 mum; sub lV fast-transient-response output-capacitor-free LDO regulator; time 1.6 s; transient state; voltage 0.9 V; voltage 200 mV; Capacitors; Logic gates; Operational amplifiers; Regulators; Transient analysis; Transient response; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467696

Filename

6467696