DocumentCode
3417376
Title
A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]
Author
Choi, J. ; Chun, S. ; Na, N. ; Swaminathan, M. ; Smith, L.
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2000
fDate
2000
Firstpage
156
Lastpage
161
Abstract
This paper discusses a method for computing the effect of decoupling capacitors on the power delivery system for gigahertz packages and boards. A fast and accurate computational method is presented that can be used to estimate the amount of decoupling required, the type of capacitor to be used and its location (on-chip, package or board)
Keywords
CMOS integrated circuits; VLSI; capacitors; circuit optimisation; integrated circuit design; integrated circuit packaging; CMOS; VLSI; computational method; decoupling capacitors; gigahertz systems; packages; power delivery system; Capacitors; Circuit noise; Clocks; Frequency; Impedance; Optimization methods; Packaging; Power engineering computing; Semiconductor device noise; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location
Calcutta
ISSN
1063-9667
Print_ISBN
0-7695-0487-6
Type
conf
DOI
10.1109/ICVD.2000.812602
Filename
812602
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