DocumentCode
3417405
Title
Increasing the speed and saving multipliers in block parallel digital filters by a linear transformation
Author
Wintermantel, Markus ; Lüder, Ernst
Author_Institution
Inst. fur Netwerk- und Systemtheorie, Stuttgart Univ., Germany
Volume
2
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
81
Abstract
The linear transformation of flow graph matrices of block parallel digital filters can be applied to increase the speed of operation and to reduce the number of multipliers. To this aim we introduce a convenient matrix representation of block parallel digital filters and explain the transformation. As an example a second order block parallel filter with arbitrary block length L is generated which has the same high speed as an equivalent block-state space filter, but a multiplier complexity linear in block length L instead of square. For L=3 the number of multipliers is reduced by 32% compared with the block-state space filter and for L=6 by 26% compared with the structure proposed by Parhi
Keywords
Circuits; Digital filters; Dynamic range; Equations; Flow graphs; Nonlinear filters; Polynomials; Signal generators; Transfer functions; Transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408910
Filename
408910
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