Title :
Manufacturability and testability oriented synthesis
Author :
Shaikh, S.A. ; Khare, J. ; Heineken, H.T.
Author_Institution :
DFM Group, Level One Commun. Inc., Sacramento, CA, USA
Abstract :
This paper presents a case for new generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect field model, which estimates yield as a function of netlist attributes. Testability oriented synthesis encompasses various design-for-test (DFT), synthesis for testability, (SFT) and the high-level test synthesis (HLTS) techniques during the synthesis process
Keywords :
circuit optimisation; design for manufacture; design for testability; high level synthesis; integrated circuit interconnections; timing; SoC; die-area; high-level test synthesis; interconnect field model; manufacturability; netlist attributes; optimization factors; synthesis for testability; synthesis too; testability oriented synthesis; timing; Application specific integrated circuits; Cost function; Design for manufacture; Design for testability; Manufacturing processes; System-on-a-chip; Testing; Timing; Transistors; Yield estimation;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812607
