A transistor level placement tool for custom cell generation

Author

Dash, Ranjit K. ; Pramod, T. ; Vasudevan, V. ; Ramakrishna, M.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India

fYear

2000

fDate

2000

Firstpage

254

Lastpage

257

Abstract

In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; simulated annealing; CMOS ICs; Eulerian path finding algorithm; VLSI layout; custom cell generation; macro cell design style; optimisation tool; simulated annealing; transistor level placement tool; CMOS logic circuits; CMOS technology; Circuit simulation; Costs; Libraries; Parasitic capacitance; Programmable logic arrays; Simulated annealing; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2000. Thirteenth International Conference on

Conference_Location

Calcutta

ISSN

1063-9667

Print_ISBN

0-7695-0487-6

Type

conf

DOI

10.1109/ICVD.2000.812617

Filename

812617