Title :
On the transistor sizing problem
Author_Institution :
Motorola India Electron. Ltd., Bangalore, India
Abstract :
This paper introduces a new transistor sizing technique for timing optimization in a transistor level netlist. Starting from an initial solution, the widths of the transistors in the netlist are tuned iteratively to meet the specified timing constraints. Efficient heuristics to significantly improve the run time performance are outlined. The improvement of timing and area performance are demonstrated with several real circuits
Keywords :
VLSI; circuit layout CAD; circuit optimisation; delay estimation; digital integrated circuits; integrated circuit layout; timing; area performance improvement; heuristics; run time performance; specified timing constraints; timing optimization; timing performance improvement; transistor level netlist; transistor sizing technique; Circuit simulation; Constraint optimization; Cost function; Delay; Linear programming; Optimization methods; Runtime; Simulated annealing; Timing; Transistors;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812618
