A distributed memory and control architecture for 2D discrete wavelet transform

Author

Singh, J. ; Antoniou, A. ; Shpak, D.J.

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

Volume

3

fYear

1999

fDate

36342

Firstpage

387

Abstract

A distributed memory and control architecture for parallel computation of the 2D discrete wavelet transform is proposed. The architecture is systolic and is obtained by performing a thorough data dependence and localization analysis for the 2D discrete wavelet transform. The design is modular, and can easily be scaled for different levels of wavelet decomposition and filter lengths. The derived architecture for an 8×8 image has been functionally verified and a chip layout has been obtained in Cadence

Keywords

discrete wavelet transforms; distributed memory systems; image sequences; pipeline processing; systolic arrays; 2D discrete wavelet transform; Cadence; chip layout; data dependence; distributed memory architecture; filter lengths; localization analysis; parallel computation; wavelet decomposition; Computer architecture; Concurrent computing; Discrete wavelet transforms; Distributed computing; Distributed control; Filter bank; Memory architecture; Signal resolution; Systolic arrays; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.778866

Filename

778866