• DocumentCode
    3417693
  • Title

    A tight area upper bound for slicing floorplans

  • Author

    Peixoto, Helvio P. ; Jacome, Margarida F. ; Royo, Ander

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    280
  • Lastpage
    285
  • Abstract
    The ability to perform reliable early estimation is essential to support early design space exploration. In this paper we present a tight upper bound for the area of slicing floorplans. The proposed formulation outperforms the best known bounds on a set of practical/realistic floorplanning scenarios. Previous work has shown that slicing floorplans can be quite efficient in packing modules tightly, and thus the relevance of our proposed area estimate
  • Keywords
    VLSI; estimation theory; integrated circuit layout; VLSI layout; area estimation; area upper bound; design space exploration; slicing floorplans; Algorithm design and analysis; Delay estimation; Ear; Heuristic algorithms; Mathematical analysis; Shape; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2000. Thirteenth International Conference on
  • Conference_Location
    Calcutta
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-0487-6
  • Type

    conf

  • DOI
    10.1109/ICVD.2000.812622
  • Filename
    812622