Title :
Design for strong testability of RTL data paths to provide complete fault efficiency
Author :
Wada, Hiroki ; Masuzawa, Toshimitsu ; Saluja, Kewal K. ; Fujiwara, Hideo
Author_Institution :
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Ikoma, Japan
Abstract :
In this paper, we propose a DFT method for RTL data paths to achieve 100% fault efficiency. The DFT method is based on hierarchical test and usage of a combinational ATPG tool. The DFT method requires lower hardware overhead and shorter test generation time than the full scan method, and also improves test application time drastically compared with the full scan method
Keywords :
VLSI; automatic test pattern generation; data flow graphs; design for testability; fault diagnosis; high level synthesis; logic testing; VLSI; combinational ATPG tool; complete fault efficiency; design for strong testability; hierarchical test; lower hardware overhead; register transfer level data paths; shorter test generation time; stuck-at faults; test application time; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design for testability; Design methodology; Hardware; Iron; Latches; Test pattern generators;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812625
