• DocumentCode
    3417782
  • Title

    Novel achievements in the understanding and suppression of parasitic minority carrier currents in P- epitaxy/P++ substrate smart power technologies

  • Author

    Stella, R. ; Favilla, S. ; Croce, G.

  • Author_Institution
    STMicroelectronics, Cornaredo, Italy
  • fYear
    2004
  • fDate
    24-27 May 2004
  • Firstpage
    423
  • Lastpage
    426
  • Abstract
    In this paper, parasitic electron currents in P-/P++ substrates are thoroughly investigated by the results of numerical simulations, the predictions of an analytical model, and experiments. An optimization of the protection technique, which does not require the addition of a deep trench isolation, and allows similar results in the suppression of the parasitic currents, is proposed.
  • Keywords
    circuit optimisation; integrated circuit design; integrated circuit modelling; minority carriers; power integrated circuits; substrates; P-/P++ substrates; parasitic electron currents; parasitic minority carrier current suppression; protection technique optimization; smart power technologies; Charge carrier processes; Circuit optimization; Integrated circuit design; Integrated circuit modeling; Power integrated circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD '04. The 16th International Symposium on
  • Print_ISBN
    4-88686-060-5
  • Type

    conf

  • DOI
    10.1109/ISPSD.2004.1332965
  • Filename
    1332965
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3417782