Title :
Automatic validation test generation using extracted control models
Author :
Sumners, Rob ; Bhadra, Jayanta ; Abraham, Jacob
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
We present a procedure for the automatic generation of tests covering control states of a sequential circuit. The procedure consists of extracting a control model of the circuit under test and then using this model to guide the search for concrete executions or witnesses. We present results of experiments using the procedure on a communication chip from industry as well as an implementation of the ARM 2 processor
Keywords :
circuit testing; logic testing; sequential circuits; ARM 2 processor; automatic validation test generation; circuit testing; communication chip; extracted control models; sequential circuit; witness generation; Automatic generation control; Automatic testing; Circuit testing; Communication industry; Concrete; Hip; Jacobian matrices; Read only memory; Sequential analysis; Sequential circuits;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812627
