Title :
Optimisation of the one-dimensional full search algorithm and implementation using an EPLD
Author :
Rajaram, Rajesh T N ; Vasudevan, Vinita
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
Abstract :
This paper presents a technique for the modification and optimisation of the one-dimensional full search (IDFS) motion estimation algorithm. The modified version of the IDFS algorithm has desirable properties for efficient hardware implementation. The spatial redundancy between the motion vectors of the macroblocks within a frame is exploited for the purpose of optimisation. The performance of the proposed technique is competitive, as compared to the more popular hierarchical three step search (TSS) method. The speed of the proposed technique, when implemented in hardware, is higher than the TSS method. The results of an implementation in an EPLD, targeted for real time operation, are given
Keywords :
VLSI; circuit optimisation; computer architecture; digital signal processing chips; integrated circuit design; motion estimation; programmable logic arrays; redundancy; EPLD; IDFS algorithm; VERILOG; block matching algorithm; embedded programmable logic devices; hierarchical three step search; macroblocks; motion estimation algorithm; motion vectors; one-dimensional full search algorithm; optimisation; performance; real time; spatial redundancy; Computational complexity; Degradation; HDTV; Hardware; Hydrogen; Image coding; Motion estimation; Motion pictures; Transform coding; Video coding;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812629