Dynamic trellis diagrams for optimized DSP code generation

Author

Fröhlich, Stefan ; Gotschlich, Martin ; Krebelder, Udo ; Wess, Bernhard

Author_Institution

Inst. fur Nachrichtentech. und Hochfrequenztech., Vienna Univ. of Technol., Vienna, Austria

Volume

3

fYear

1999

fDate

36342

Firstpage

492

Abstract

In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal processors (DSPs). In contrast to static trellis diagrams (STDs), which may be precalculated, DTDs are built at runtime and adapted exactly to the local requirements. Therefore, DTDs are more flexible and need less program memory. Due to the significant reduction in memory size, the increase of compilation time is only moderate. At present, the concept of DTDs has been successfully applied to DFG compiler implementations for a variety of general purpose DSP families, including Motorola´s DSP56000 and Analog Devices´ ADSP-2100

Keywords

data flow graphs; digital signal processing chips; program compilers; Analog Devices ADSP-2100; Motorola DSP56000; automatic translation; compilation time; data flow graphs; dynamic trellis diagrams; local requirements; memory size; optimized DSP code generation; Artificial intelligence; Assembly; Code standards; Compaction; Digital signal processing; Flow graphs; Optimizing compilers; Program processors; Registers; Tree graphs;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.778890

Filename

778890