A novel system architecture for real-time low-level vision

Author

Benedetti, A. ; Perona, P.

Author_Institution

Div. of Eng. & Appl. Sci., California Inst. of Technol., Pasadena, CA, USA

Volume

3

fYear

1999

fDate

36342

Firstpage

500

Abstract

A novel system architecture that exploits the spatial locality in memory access that is found in most low-level vision algorithms is presented. A real-time feature selection system is used to exemplify the underlying ideas, and an implementation based on commercially available field programmable gate arrays (FPGAs) and synchronous SRAM memory devices is proposed. The peak memory access rate of a system based on this architecture is estimated at 2.88 G-Bytes/s, which represents a four to five times improvement with respect to existing reconfigurable computers

Keywords

computer vision; feature extraction; field programmable gate arrays; real-time systems; reconfigurable architectures; video signal processing; field programmable gate arrays; memory access; real-time feature selection system; real-time low-level vision; spatial locality; synchronous SRAM memory devices; system architecture; Application software; Bandwidth; Computer architecture; Costs; Field programmable gate arrays; Machine vision; Pixel; Random access memory; Real time systems; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.778892

Filename

778892