DocumentCode :
3417933
Title :
Capturing the effect of crosstalk on delay
Author :
Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
2000
fDate :
2000
Firstpage :
364
Lastpage :
369
Abstract :
Crosstalk is generally recognized as a major problem in IC design. This paper presents a novel approach to the efficient measurement of the effect of crosstalk on the delay of a net using an algorithm whose worst-case complexity is polynomial-time in the number of nets. The cost of the algorithm is seen to be O(nlogn) in practice, where n is the number of nets, and it is amenable to being incorporated into the inner loop of a timing optimizer. To illustrate this, the method is applied to reduce the effects of crosstalk in channel routing, where it is seen to give an average improvement of 23% in the delay in a channel as compared to the worst case, as measured by SPICE
Keywords :
SPICE; circuit optimisation; crosstalk; integrated circuit design; network routing; timing; IC design; SPICE; channel routing; crosstalk; delay; polynomial-time complexity; timing optimizer; worst-case complexity; Circuits; Crosstalk; Delay effects; Electrical capacitance tomography; Hoses; Phase estimation; Routing; Time measurement; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
ISSN :
1063-9667
Print_ISBN :
0-7695-0487-6
Type :
conf
DOI :
10.1109/ICVD.2000.812634
Filename :
812634
Link To Document :
بازگشت