Title :
Resource-constrained compaction of sequential circuit test sets
Author :
Bommu, Surendra K. ; Chakradhar, Srimat T. ; Doreswamy, Kiran B.
Author_Institution :
Synopsys Inc., Boston, MA, USA
Abstract :
We investigate a new, resource-constrained method for static compaction of large, sequential circuit test sets. Our approach is based on two key observations: (1) since all physical defects cannot be covered using a single defect model, test sets include tests generated using multiple defect models like stuck-at, delay, or bridging fault models. Therefore, it is unlikely that a marginal drop (0.5% or less) in fault coverage during compaction of tests generated for a single defect model will adversely affect the test quality of the overall test set. (2) Fault coverage is an aggregate measure that can be preserved as long as the original and compacted test sets detect the same number of faults. The specific faults detected by the two test sets can be significantly different. In particular, the compacted vector set may detect new faults that are not detected by the original vector set. The new compaction technique was implemented as part of the recently proposed two-phase static compaction technique. Experimental results on ISCAS benchmarks and several production circuits show that: (1) the actual loss in fault coverage, if any, was significantly less than the pre-specified tolerance limit of 1%; (2) fault coverage of the compacted test set can be higher than the original test set; and (3) significantly higher compaction is achieved using fewer CPU seconds, as compared to the baseline system that compacts test sets to preserve fault coverage
Keywords :
automatic test software; circuit analysis computing; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; C program; CPU time reduction; SCOPE program; compacted vector set; defect models; fault coverage; large test sets; resource-constrained compaction; sequential circuit test sets; static compaction; two-phase static compaction technique; Aggregates; Circuit faults; Circuit testing; Compaction; Delay; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; System testing;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812640