DocumentCode :
3418039
Title :
Dataflow analysis for resource contention and register leakage properties
Author :
Roy, Subir K. ; Iwashita, Hiroaki ; Nakata, Tsuneo
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear :
2000
fDate :
2000
Firstpage :
418
Lastpage :
423
Abstract :
Resource contention and register leakage are two important classes of properties which need to be verified in every design to identify difficult bugs. They can be derived automatically from the RTL implementation model. In this paper, an approach for their systematic formulation is given. The automated approach unburdens the verification team from the tedious process of formulating them, thereby, allowing focus on the formulation of other important properties
Keywords :
circuit analysis computing; data flow analysis; formal verification; logic CAD; RTL implementation model; dataflow analysis; register leakage properties; resource contention; systematic formulation; verification; Data analysis; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
ISSN :
1063-9667
Print_ISBN :
0-7695-0487-6
Type :
conf
DOI :
10.1109/ICVD.2000.812643
Filename :
812643
Link To Document :
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