DocumentCode
3418066
Title
A low-power high reliability CMOS current limit circuit
Author
Xiao-jie, Cheng ; Quan-yuan, Feng
Author_Institution
Microelectron. Inst., Southwest Jiaotong Univ., Chengdu, China
Volume
5
fYear
2005
fDate
4-7 Dec. 2005
Abstract
A low-power high reliability CMOS current limit circuit is proposed, which can lower the circuit´s power dissipation, and enhance the reliability of the system with the application of foldback current limit circuit. This circuit is manufactured by normal 0.6μm CMOS technology. The Hspice simulation results proved the feasibility of the circuit.
Keywords
CMOS analogue integrated circuits; current limiters; integrated circuit reliability; low-power electronics; 0.6 micron; circuit reliability; foldback current limit circuit; low power CMOS current limit circuit; power dissipation; CMOS technology; Circuit simulation; Insulated gate bipolar transistors; MOSFETs; Manufacturing; Microelectronics; Power dissipation; Power system reliability; Resistors; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings
Print_ISBN
0-7803-9433-X
Type
conf
DOI
10.1109/APMC.2005.1607114
Filename
1607114
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