Title :
Performance improvement of Si Pocket-Tunnel FET with steep subthreshold slope and high ION/IOFF ratio
Author :
Qianqian Huang ; Ru Huang ; Zhan Zhan ; Chunlei Wu ; Yingxin Qiu ; Yangyuan Wang
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
fDate :
Oct. 29 2012-Nov. 1 2012
Abstract :
In this paper, we have experimentally demonstrated an all-Si Pocket-Tunnel FET (Pocket-TFET) with steep subthreshold slope (SS) of 52mV/dec and high ION/IOFF ratio of 3.9×106 based on the bulk silicon substrate by CMOS compatible process. It is the best experimental performance in the published silicon-based TFETs with a fully-depleted doping pocket layer at the source/channel interface. Compared with traditional TFET, through changing the drain layout, the extremely abrupt tunnel junction can be well achieved with the source pocket, resulting in the superior SS and ION. In addition, the ambipolar effect can be also greatly reduced in the fabricated Pocket-TFET.
Keywords :
CMOS integrated circuits; elemental semiconductors; field effect transistors; silicon; tunnel transistors; CMOS compatible process; Si; bulk silicon substrate; drain layout; fabricated pocket-TFET; fully-depleted doping pocket layer; high ION-IOFF ratio; silicon pocket-tunnel FET; source pocket; source-channel interface; steep subthreshold slope; tunnel junction; Current measurement; Doping; Junctions; Logic gates; Silicon; Temperature; Tunneling;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
DOI :
10.1109/ICSICT.2012.6467740
