Title :
Characterization of the wafer dicing process using Taguchi methodology
Author :
Shah, Harry ; Ram, Satish
Author_Institution :
Motorola Inc., Chandler, AZ, USA
fDate :
30 Sep-1 Oct 1992
Abstract :
The use of Taguch´s method of experimental design to characterize the wafer dicing process and improve the yield by reducing backside damage is described. It is shown how the orthogonal array was modified to accommodate mixed levels. Analysis of variance (ANOVA) was used to identify the significant factors. Using the optimum levels of the significant factors resulted in over 85% reduction in scrap, and 60% reduction in dicing process cycle time due to elimination of an inspection operation
Keywords :
cutting; data analysis; integrated circuit manufacture; Taguchi methodology; analysis of variance; backside damage-reduction; mixed levels; orthogonal array; scrap reduction; semiconductor wafers; wafer dicing process; Analysis of variance; Application specific integrated circuits; Assembly; Blades; Computer aided manufacturing; Costs; High performance computing; Integrated circuit manufacture; Semiconductor device manufacture; Silicon;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1992. ASMC 92 Proceedings. IEEE/SEMI 1992
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-0740-2
DOI :
10.1109/ASMC.1992.253792
