DocumentCode :
3418235
Title :
SOI digital circuits: design issues
Author :
Puri, Ruchir ; Chuang, C.T.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2000
fDate :
2000
Firstpage :
474
Lastpage :
479
Abstract :
This paper reviews the recent advances in SOI digital CMOS circuits. Particular emphases is placed on the impact of floating-body in partially-depleted devices on the circuit operation, stability, and functionality. Unique SOI design aspects such as parasitic bipolar effect and hysteretic VT variation are addressed. Circuit techniques to improve the noise immunity and global design issues are also addressed
Keywords :
CMOS digital integrated circuits; circuit stability; integrated circuit design; integrated circuit noise; silicon-on-insulator; SOI digital circuits; circuit operation; digital CMOS circuits; floating-body; functionality; global design issues; hysteretic VT variation; noise immunity; parasitic bipolar effect; partially-depleted devices; stability; CMOS digital integrated circuits; CMOS technology; Circuit noise; Circuit stability; Digital circuits; Hysteresis; Immune system; Microprocessors; Scalability; Semiconductor films;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
ISSN :
1063-9667
Print_ISBN :
0-7695-0487-6
Type :
conf
DOI :
10.1109/ICVD.2000.812652
Filename :
812652
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3418235
بازگشت