Title :
Jitter estimation methodology for clock chips
Author :
Maheshwari, Sanjeev Kumar ; Visweswaran, G.S. ; Krishanan, R.S.
Author_Institution :
CYPRESS Semicond., India Design Center, Bangalore, India
Abstract :
A simulation methodology is developed for clock chips to predict their AC performance more accurately. Power bus modeling is shown to lead to more accurate and predictable jitter values. Jitter variation is plotted for a typical set of 2CPU-7PCI simultaneously switching pads, for the variation in inductance, capacitive load and frequency
Keywords :
circuit simulation; clocks; inductance; integrated circuit modelling; jitter; pulse generators; 2CPU-7PCI simultaneously switching pads; AC performance; capacitive load; clock chips; frequency; inductance; jitter estimation methodology; jitter values; jitter variation; power bus modeling; simulation methodology; Circuit noise; Clocks; Frequency; Inductance; Jitter; Logic circuits; Phase locked loops; Position measurement; Predictive models; Semiconductor device noise;
Conference_Titel :
VLSI Design, 2000. Thirteenth International Conference on
Conference_Location :
Calcutta
Print_ISBN :
0-7695-0487-6
DOI :
10.1109/ICVD.2000.812653
