• DocumentCode
    3418379
  • Title

    Impact of pattern density on plasma damage of CMOS LSIs

  • Author

    Miyamoto, K. ; Nakamura, J. ; Hatanaka, K. ; Hashimoto, T. ; Tamura, I. ; Maeda, T. ; Sato, K. ; Kakumu, M.

  • Author_Institution
    LSI Div., Toshiba Corp., Kawasaki, Japan
  • fYear
    1996
  • fDate
    8-11 Dec. 1996
  • Firstpage
    739
  • Lastpage
    742
  • Abstract
    This paper proposes a new plasma damage model that can explain and estimate the plasma damage in a CMOS LSI by taking into account the additional factor of pattern density. Reliability data presented in this paper shows that plasma damage to MOSFET gate oxide in a CMOS LSI cannot be fully explained by considering only antenna and aspect ratio theory. To verify the model on a CMOS LSI, a test pattern was designed with three parameters; antenna ratio, aspect ratio and pattern density. It is concluded that CMOS LSI reliability results were explained by this new model. This model should be taken into account when designing CMOS LSI circuits to avoid damage by plasma processes.
  • Keywords
    CMOS integrated circuits; integrated circuit modelling; integrated circuit reliability; large scale integration; CMOS LSI; LSI reliability; MOSFET gate oxide; antenna ratio; aspect ratio; pattern density; plasma damage model; reliability data; CMOS process; Circuits; Large scale integration; Plasma applications; Plasma density; Plasma devices; Plasma measurements; Semiconductor device modeling; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1996. IEDM '96., International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-3393-4
  • Type

    conf

  • DOI
    10.1109/IEDM.1996.554086
  • Filename
    554086