DocumentCode :
3418474
Title :
A temporal logic for input output symbolic transition systems
Author :
Aiguier, Marc ; Gaston, Christophe ; Le Gall, Pascale ; Longuet, Delphine ; Touil, Assia
Author_Institution :
LaMI, Univ. d´´Evry, Evry, France
fYear :
2005
fDate :
15-17 Dec. 2005
Abstract :
In this paper, we present a temporal logic called ℱ whose interpretation is over input output symbolic transition systems (IOSTS). IOSTS extend transition systems to communications and data in order to tackle communications with system environment. ℱ is then defined as an extension of temporal logic CTL* (a temporal logic which mixes together the features of linear temporal logic (LTL) and computational temporal logic (CTL)). Three basic properties are established on ℱ: adequacy and preservation of properties along synchronized product and IOSTS refinement.
Keywords :
bisimulation equivalence; formal specification; formal verification; temporal logic; CTL; LTL; bisimulation equivalence; computational temporal logic; formal specification; formal verification; input output symbolic transition system; linear temporal logic; Automatic testing; Context; Logic testing; Mathematical model; Nuclear power generation; Performance evaluation; Refining; Safety; Software engineering; System testing; adequacy; input output symbolic transition systems; refinement; strong bisimulation; temporal logic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software Engineering Conference, 2005. APSEC '05. 12th Asia-Pacific
ISSN :
1530-1362
Print_ISBN :
0-7695-2465-6
Type :
conf
DOI :
10.1109/APSEC.2005.19
Filename :
1607135
Link To Document :
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