Title :
Reliability and power management of integrated systems
Author :
Mihic, Kresimir ; Simunic, Tajana ; De Micheli, Giovanni
Author_Institution :
CSL, Stanford Univ., CA, USA
fDate :
31 Aug.-3 Sept. 2004
Abstract :
A new approach for dynamic reliability and power management of integrated systems, such as systems on chips (SoCs) and networks in chips (NoCs) is presented. With aggressive transistor scaling, decreased voltage margins, and increased processor power and temperature, reliability assessment has become a significant issue in design. Our work combines for the first time dynamic power management with reliability models. The joint model is used to determine system level reliability as a function of failure rates, system configuration and power management policies. We show that the overall system reliability is strongly affected by reliability network topology and power management policy.
Keywords :
circuit simulation; integrated circuit design; integrated circuit reliability; network topology; system-on-chip; SOC; circuit design; dynamic reliability; failure rate; integrated systems; network topology; networks in chips; power management; processor power; processor temperature; system configuration; systems on chips; transistor scaling; voltage margin; Dynamic voltage scaling; Energy consumption; Energy management; Network-on-a-chip; Power system management; Power system modeling; Power system reliability; Runtime; System-on-a-chip; Topology;
Conference_Titel :
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN :
0-7695-2203-3
DOI :
10.1109/DSD.2004.1333252
