An efficient hierarchical fault isolation technique for mixed-signal boards

In this paper, we describe a technique for hierarchical fault isolation in analog and mixed-signal circuit boards. The technique is based on verifying the fault-free behavior of partitions of the circuit, and can be applied hierarchically to large systems. The technique is shown to be independent of the availability/completeness of fault models for the circuit-under-test (CUT). Also, it has minimal on-line computational requirements and can be easily programmed on an automatic tester. Experimental results to show the effectiveness of the technique are presented