A novel design for the construction and startup of an eight inch pilot line

Author

Tseng, Bob H P ; Cheng, Chih-Hsiung ; Chen, H.H. ; Lu, C.Y. ; Jensen, Robert

Author_Institution

Electron. Res. & Service Org., Hsinchu, Taiwan

fYear

1992

fDate

30 Sep-1 Oct 1992

Firstpage

60

Lastpage

65

Abstract

An 8-in wafer line with 0.5-μm CMOS process technology for DRAM and SRAM pilot production is discussed. The pilot line is expected to achieve: (1) speedy construction and startup with overall duration of 16 months; (2) a class-0.1 clean environment at 0.3-μm particle testing level; (3) the flexibility to advance to 0.2-μm process technology when needed; (4) the flexibility to enlarge the processing capacity to mass production level (if needed) without interrupting pilot line production. Principles of this design are outlined, difficulties encountered on implementation are discussed, solution approaches employed are illustrated, and preliminary startup results are presented

Keywords

CMOS integrated circuits; DRAM chips; SRAM chips; clean rooms; integrated circuit manufacture; 0.2 to 0.5 micron; CMOS process technology; DRAM; SRAM; clean environment; mass production level; particle testing level; pilot line; startup results; wafer line; CMOS process; CMOS technology; Construction industry; Consumer electronics; Costs; Isolation technology; Manufacturing industries; Random access memory; Semiconductor device manufacture; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 1992. ASMC 92 Proceedings. IEEE/SEMI 1992

Conference_Location

Cambridge, MA

Print_ISBN

0-7803-0740-2

Type

conf

DOI

10.1109/ASMC.1992.253837

Filename

253837