ASSEC: an asynchronous self-checking RISC-based processor

The use of deep submicron technology raises a number of concerns about reliability in VLSI circuits. Shrinking geometries and reduced power supplies leave the circuits vulnerable to ´soft´ and transient errors. The combination of high clock speed and large circuit area result in high power consumption and skew in clock distribution. This paper investigates the use of concurrent error detection (CED) and asynchronous design to overcome these problems. Four pipelined processor designs are compared - two synchronous, two asynchronous with one of each type using CED. Initial results indicate an area overhead of 12% in return for a fault coverage of 98.54% of all unidirectional errors. Additionally, the asynchronous CED processor has an area overhead of only 4% when compared to the synchronous nonCED design.