Investigating available instruction level parallelism for stack based machine architectures

Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming language for Internet, and more recently in embedded applications. However, instruction level parallelism (ILP) has not yet received significant attention with respect to such machines. We have developed a stack code viewer/analyzer tool to analyze available ILP in stack assembler-code, together with the UTSA simulator, under unlimited software and hardware resource configurations. Results for basic block analysis reveal marginal speedups of available ILP over the serial execution in the absence of mechanisms for branch speculation or code optimization. Results for superblock and loop unrolling techniques show that more significant improvements can be made to available parallelism where effort is directed. An experiment is also presented to highlight the significance of branch prediction. In all tests, our stack code viewer/analyzer tool can graphically represent the scheduling result of each basic block.