Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)

Author

Tai-Su Park ; Yu Gyun Shin ; Han Sin Lee ; Moon Han Park ; Sang Dong Kwon ; Ho Kyu Kang ; Young Bum Koh ; Moon Yong Lee

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

747

Lastpage

750

Abstract

In order to develop a Shallow Trench Isolation (STI) which does not have trench corner induced degradation of the gate oxide, its integrities were evaluated with rounded, non-rounded top corner, and an addition of CVD SiO/sub 2/ spacer. In the experiment, we found that the rounded and SiO/sub 2/ spacered STI showed the best result meaning no harmful influence of the corner to the gate oxide integrity. Also, etch-back processes of the filled CVD SiO/sub 2/ were modified to eliminate the degradation of the gate oxide by a stress concentration at top corner kinks.

Keywords

MOSFET; etching; isolation technology; oxidation; semiconductor device reliability; stress analysis; CVD SiO/sub 2/ spacer; NMOS transistor; Si-SiO/sub 2/-SiN; charge to breakdown; chemical mechanical polishing planarization; etch-back processes; gate oxide integrity; gate oxide reliability; nonrounded top corner; rounded top corner; shallow trench isolation; stress concentration; stress simulation; top corner kinks; trench top corner profile; Chemical vapor deposition; Degradation; Etching; Filling; Hafnium; Moon; Planarization; Research and development; Silicon compounds; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554088

Filename

554088