DocumentCode
3418850
Title
A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder
Author
Ciao, P. ; Colavolpe, G. ; Fanucci, L.
Author_Institution
Dept. of Inf. Eng., Pisa Univ., Italy
fYear
2004
fDate
31 Aug.-3 Sept. 2004
Firstpage
174
Lastpage
181
Abstract
This paper presents a 2048 bit, rate 1/2 soft decision decoder for a new class of codes known as turbo Gallager codes. The decoder can support up to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 μm standard-cell CMOS technology.
Keywords
CMOS digital integrated circuits; VLSI; codecs; integrated circuit design; iterative decoding; parallel architectures; turbo codes; 0.18 micron; 1 Gbit/s; 2048 bit; CMOS technology; VLSI architecture; parallel architecture; turbo Gallager code decoder; Bit error rate; CMOS technology; Convolutional codes; Councils; Hardware; Iterative decoding; Parity check codes; Throughput; Turbo codes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN
0-7695-2203-3
Type
conf
DOI
10.1109/DSD.2004.1333274
Filename
1333274
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