DocumentCode :
3418906
Title :
Shift invert coding (SINV) for low power VLSI
Author :
Natesan, Jayapreetha ; Radhakrishnan, Damu
Author_Institution :
Dept. of Electr. & Comput. Eng., New York State Univ., New Paltz, NY, USA
fYear :
2004
fDate :
31 Aug.-3 Sept. 2004
Firstpage :
190
Lastpage :
194
Abstract :
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transitions on the bus and bus invert coding is a widely popular technique for that. In this paper we introduce a new way of coding called the ShiftInv coding that is superior to the bus invert coding technique. Our simulation results show a considerable reduction on the number of transitions over and above that obtained with bus invert coding. Further, the proposed technique requires only 2 extra bits for the low power coding, regardless of the bit-width of the bus and does not assume anything about the nature of the data.
Keywords :
CMOS logic circuits; VLSI; encoding; logic design; logic simulation; low-power electronics; CMOS circuit; ShiftInv coding; VLSI circuit design; bus invert coding; bus transition; low power circuit; low power coding; shift invert coding; CMOS technology; Circuit simulation; Circuit synthesis; Data buses; Hardware; Mobile computing; Reflective binary codes; Terminology; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN :
0-7695-2203-3
Type :
conf
DOI :
10.1109/DSD.2004.1333276
Filename :
1333276
Link To Document :
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