Image processing algorithms on reconfigurable architecture using HandelC

Computer manipulation of images is generally defined as digital image processing (DIP). DIP is employed in variety of applications, including video surveillance, target recognition, and image enhancement. Some of the algorithms used in image processing include convolution, edge detection and contrast enhancement. These are usually implemented in software but may also be implemented in special purpose hardware to reduce speed. In this work the canny edge detection [A computational approach to the edge detection] architecture has been developed using reconfigurable architecture and hardware modeled using a C-like hardware language called Handel-C. The proposed architecture is capable of producing one edge-pixel every clock cycle. The hardware modeled was implemented using the DK2 IDE tool on the RC1000 Xilinx Vertex FPGA based board. The algorithm was tested on standard image processing benchmarks and significances of the result are discussed.