• DocumentCode
    3419171
  • Title

    A constraints programming approach to communication scheduling on SoPC architectures

  • Author

    Wolinski, Christophe ; Kuchcinski, Krzysztof ; Gokhale, Maya

  • Author_Institution
    IRISA, IFSIC, France
  • fYear
    2004
  • fDate
    31 Aug.-3 Sept. 2004
  • Firstpage
    308
  • Lastpage
    315
  • Abstract
    This paper presents a method to obtain an optimized static schedule of CSP-like communications between a collection of concurrent hardware processes implemented on "system on a programmable chip" (SoPC). The hardware processes are the applications tailored "cells" in the processor-coupled polymorphous fabric (Wolinski et al., 2003 and Wolinski et al., 2002) implemented on the Altera Excalibur Arm SoPC platform. In our global approach, a static communications schedule is adopted to reduce hardware overhead due to inter-cells message transfer synchronization and to speed-up application execution. The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal communication schedules in a number of real cases. It makes also possible to easily generate pipelined schedules that improve significantly performance of the final implementation. Our method is illustrated with a fabric-based implementation of the K-means clustering algorithm. An optimal communication scheduled is achieved for this application.
  • Keywords
    communicating sequential processes; constraint handling; processor scheduling; programmable circuits; system-on-chip; Altera Excalibur Arm SoPC platform; K-means clustering algorithm; SoPC architectures; communication scheduling; constraints programming; message transfer synchronization; pipelined schedules; polymorphous fabric; scheduling problem; static communications schedule; system on a programmable chip; Clustering algorithms; Communication system control; Computer architecture; Computer science; Fabrics; Hardware; Laboratories; Logic programming; Optimization methods; Processor scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design, 2004. DSD 2004. Euromicro Symposium on
  • Print_ISBN
    0-7695-2203-3
  • Type

    conf

  • DOI
    10.1109/DSD.2004.1333291
  • Filename
    1333291