Suppression of V/sub th/ fluctuation by minimizing transient enhanced diffusion for deep sub-quarter micron MOSFET

Author

Ono, A. ; Sakai, I.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

755

Lastpage

758

Abstract

It is revealed that the threshold voltage (V/sub th/) fluctuation in deep sub-quarter micron nMOSFETs is due more to variation of channel impurity concentration than to variation of gate length or oxide thickness. This is because the transient enhanced diffusion (TED) of the channel impurity becomes significant when the concentration of the interstitial Si atoms increases as gate length decrease. A rapid thermal annealing process, which minimizes the TED, is very effective in suppressing the V/sub th/ fluctuation.

Keywords

MOSFET; diffusion; impurity distribution; rapid thermal annealing; voltage distribution; 0.18 mum; 850 to 1000 C; channel impurity concentration variation; deep sub-quarter micron nMOSFET; gate length; interstitial Si atom concentration; rapid thermal annealing process; threshold voltage fluctuation suppression; transient enhanced diffusion minimization; Annealing; Capacitance-voltage characteristics; Electrical resistance measurement; Fluctuations; Furnaces; Impurities; Length measurement; Lithography; MOSFET circuits; Thickness measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554090

Filename

554090