• DocumentCode
    3419351
  • Title

    A novel NAND Flash memory controller compatible with asynchronous and source synchronous data types

  • Author

    Peng Qiang ; Jian Cao ; Xing Zhang ; Dun-Shan Yu

  • Author_Institution
    Sch. of Software & Microelectron., Peking Univ., Beijing, China
  • fYear
    2012
  • fDate
    Oct. 29 2012-Nov. 1 2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    NAND Flash memory is one of the most popular memory storages which can provide two different data types - the asynchronous type and the source synchronous type. But most of the current NAND Flash controllers can only support one of these two types. This leads to incompatible in some data storage applications. This paper proposes a new circuitry structure which can support both of the source synchronous type and the asynchronous type. The circuitry is implemented in Verilog HDL and the FPGA prototype verification scheme is designed base on the Xilinx Virtex-5 XC5VLX330 platform. The prototype verification results denote that in the asynchronous data interface type, the read speed is 54.23Mb/s and the write speed is 24.12Mb/s, and in the source synchronous data interface type, the read speed reaches 96.54Mb/s and the write speed reaches 47.22Mb/s. The layout design has been accomplished with TSMC 0.13um CMOS process using Design Compiler. The area of this design is 31217.4μm2, the dynamic power is 764.523μw and the leakage power is 0.087μw.
  • Keywords
    CMOS logic circuits; NAND circuits; asynchronous circuits; flash memories; Design Compiler; FPGA prototype verification scheme; NAND flash memory controller; TSMC CMOS process; Verilog HDL; Xilinx Virtex-5 XC5VLX330 platform; asynchronous data interface type; asynchronous data type; asynchronous type; bit rate 24.12 Mbit/s; bit rate 47.22 Mbit/s; bit rate 54.23 Mbit/s; bit rate 96.54 Mbit/s; circuitry structure; data storage application; layout design; memory storage; power 0.087 muW; power 764.523 muW; size 0.13 mum; source synchronous data type; source synchronous type; CMOS process; Data transfer; Error correction codes; Flash memory; Layout; Prototypes; System-on-a-chip; 1265A; 1265D; Asynchronous EEACC: 2570A; Interface Controller; NAND Flash; Source Synchronous;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
  • Conference_Location
    Xi´an
  • Print_ISBN
    978-1-4673-2474-8
  • Type

    conf

  • DOI
    10.1109/ICSICT.2012.6467796
  • Filename
    6467796