A power clamp circuit using current mirror for on-chip ESD protection

A power clamp circuit using current mirror is proposed in this article. The current mirror is used for capacitance multiplication in the proposed circuit. Besides, the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp transistor. Simulation results verify that the proposed circuit has enhanced ability to discharge static charges during an ESD event while making the ESD pulse detection CR time constant notably smaller. With the reduction of CR time constant, the proposed circuit has better immunity to mis-triggering and is less chip area-consuming.