DocumentCode :
3419798
Title :
A parametric model checking approach for real-time systems design
Author :
Sathawornwichit, Chaiwat ; Katayama, Takuya
Author_Institution :
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
fYear :
2005
fDate :
15-17 Dec. 2005
Abstract :
Timing characteristic is a crucial point of concern in the design of real-time systems, because the systems are to operates under time-critical conditions. In this paper, we present a verification-driven approach for improving the correctness in the design of real-time systems. Our approach abstracts the details of timing information of the system by using time parameters. We propose parametric timed structure, an extension of timed transition systems, as a model for describing real-time systems. We define the parametric temporal logic PARCTL for specifying timing properties with time parameters. The model checking algorithms for parametric timed system are then proposed. The algorithms derive the necessary and sufficient condition over time parameters. We illustrate the application of our approach by deriving parameter conditions for a mutual exclusion protocol and show that the result of this approach can be used as guidelines for improving the timing correctness in the design of real-time systems.
Keywords :
automata theory; formal specification; formal verification; real-time systems; temporal logic; PARCTL parametric temporal logic; mutual exclusion protocol; parametric model checking approach; real-time systems design; timed transition systems; verification-driven approach; Application software; Automata; Computer aided manufacturing; Information science; Logic; Mathematical model; Parametric statistics; Power system modeling; Real time systems; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Software Engineering Conference, 2005. APSEC '05. 12th Asia-Pacific
ISSN :
1530-1362
Print_ISBN :
0-7695-2465-6
Type :
conf
DOI :
10.1109/APSEC.2005.12
Filename :
1607198
Link To Document :
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