A more CMOS process compatible scheme to tune the Schottky Barrier Height of NiSi to electrons by means of dopant segregation (DS) technique

Author

Jian Deng ; Jun Luo ; Chao Zhao ; Junfeng Li ; Wenwu Wang ; Dapeng Chen ; Tianchun Ye ; Hanming Wu

Author_Institution

Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

In this paper, a more CMOS process compatible scheme to tune the Schottky Barrier Height (SBH) of NiSi to electrons (φ_bn) by means of boron (B) dopant segregation (DS) technique is presented. This scheme consists of the following steps: (1) deposit Ni layers on Si substrate; (2) rapid thermal anneal (RTA1) at 300°C/60 s to form Ni-rich silicide followed by un-reacted Ni strip; (3) implant B ions into preformed Ni-rich silicide; (4) RTA2 at 450-700 °C/30 s to transform Ni-rich silicide to NiSi and to induce B DS at NiSi/Si interface as well. The φ_bn tuned using this scheme by B DS is ≥ 1.0 eV, identical to that tuned using conventional scheme by B DS, in which B ions are implanted into NiSi followed by drive-in annealing to induce B DS at NiSi/Si interface.

Keywords

CMOS integrated circuits; Schottky barriers; boron; elemental semiconductors; nickel alloys; rapid thermal annealing; segregation; silicon; silicon alloys; CMOS process compatible scheme; Ni-rich silicide; NiSi-Si; NiSi:B; Schottky barrier height; boron dopant segregation technique; drive-in annealing; implant B ion; nickel layer; rapid thermal annealing; silicon substrate; temperature 450 degC to 700 degC; Annealing; CMOS process; Electron devices; Films; Nickel; Silicides; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467834

Filename

6467834