DocumentCode
3420540
Title
A reduced surface current LDMOS with stronger ESD robustness
Author
Lingli Jiang ; Hang Fan ; Chuan He ; Bo Zhang
Author_Institution
State Key Lab. of Electron. Thin Film & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
A novel reduced surface current LDMOS structure is proposed, whose current flow is analyzed by theoretical analysis and numerical simulation. Compared to conventional LDMOS, it can restrain the surface current crowding effect under ESD stress. The TLP measured results confirms that the novel structure shows no soft leakage phenomenon, and its current discharge ability is more than four times of the conventional one.
Keywords
MOS integrated circuits; electrostatic discharge; numerical analysis; ESD robustness; TLP; current discharge ability; current flow; numerical simulation; soft leakage phenomenon; surface current LDMOS reduction; Abstracts; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467851
Filename
6467851
Link To Document