Title :
Noise tolerance enhancement in low voltage dynamic circuits
Author :
Mazumdar, Kaushik ; Pattanaik, Manisha
Author_Institution :
ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior
Abstract :
To address the noise reliability problem in deep submicron digital circuits, a new noise-tolerant dynamic circuit technique has been proposed here. The average noise threshold energy (ANTE) and the Delay normalized ANTE metrics have been used to quantify the noise immunity and speed efficiency. A 2 input AND gate has been designed and simulated using 0.18 micron BSIM3V3.3 technology to indicate that the proposed technique improves the ANTE and Delay normalized ANTE by 11.54X and 6.27X over the conventional domino circuit.
Keywords :
integrated circuit noise; integrated circuit reliability; integrated logic circuits; logic gates; low-power electronics; AND gate; BSIM3V3.3 technology; deep submicron digital circuits; delay normalized average noise threshold energy metrics; low voltage dynamic circuits; noise reliability problem; noise tolerance enhancement; speed efficiency; Circuit noise; Decision support systems; Fiber reinforced plastics; Low voltage; Virtual reality;
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-4320-8
Electronic_ISBN :
978-1-4244-4321-5
DOI :
10.1109/DTIS.2009.4938017
