A high level synthesis method for Reconfigurable Operator Array

With the complexity of IC design increasing, it becomes an emergent issue to reduce the cost and short time-t o-market of design. In this paper, we propose a high-level synthesis method for Reconfigurable Operator Array. The high-level synthesis compiler ReCom is proposed to synthesize the high-level abstract description to low-level hardware description. Meantime, three languages are proposed to implement synthesis efficiently. To prove the advantage of this method, we chose the 2 dimension 8bit s DCT algorithm as an example which consumes 1500 operators, and the sum of configuration information is 5446bits, the number of APU C code line is 29, which is much less than 389 in verilog.