Abstract :
Summary form only given. In this presentation titled Noise Issues in CMOS Devices and Circuits, state-of-art low-frequency and high-frequency noise performance and modeling in modern semiconductor devices and circuits will be discussed. The first part of the presentation will be on low-frequency noise where it will be shown that the increase of noise-to-DC current ratio may compromise circuit performance in the near future. For statistically valid experiments, it will be demonstrated that the low-frequency noise (LFN) tends to a log-normal distribution. Since the random-telegraph-signal (RTS) noise is pronounced in deep submicron devices, new techniques for characterization of multilevel RTS being observed will be discussed. The second part of the presentation will be focused on radio-frequency (RF) noise modeling of MOSFETs, including a model for the important effect of gate-tunneling current for future devices, plus sample experimental results. Then, based on the extracted active noise sources form high-frequency noise measurements, physics-based noise models for these noise sources of interest in deep submicron MOSFETs will be discussed. A simple analytic model that can be used as a guide for circuit design will be highlighted, including its scalability. The third part of the presentation will briefly introduce the subject of noise in circuits. Here, results from different types of oscillators will be discussed. Finally, the effects of hot-carrier stress on the performance of a RF voltage-controlled oscillator and a RF low-noise amplifier will be discussed.
