DocumentCode :
3420754
Title :
A Partial Irregular-Network Routing on Faulty k-ary n-cubes
Author :
Koibuchi, Michihiro ; Yoshinaga, Tsutomu ; Nishimura, Yasuhiko
Author_Institution :
National Inst. of Informatics
fYear :
2006
fDate :
Jan. 2006
Firstpage :
57
Lastpage :
64
Abstract :
Interconnection networks have been studied to connect a number of processing elements on parallel computers. Their design increasingly includes a challenge to high fault-tolerance, as entire systems become complicated. This paper presents a partial irregular-network routing in order to provide a high fault-tolerance in k-ary n-cube networks. Since an irregular-network routing usually performs poorly in k-ary n-cube networks, it is only used for progressive deadlock-recovery, and avoiding hard failures. The network is logically divided into the fault and regular regions. In the regular region, most packets are transferred along fully adaptive paths that are computed, assuming that there are no hard failures, so as to uniformly distribute the traffic. Simulation results show that the proposed routing achieves the same throughput as that of Duato´s protocol under no hard failures. As the number of faulty links increases to up to 8 on 256 nodes, its throughput is only decreased by 15%. Moreover, the throughput of the proposed deadlock-recovery routing is almost maintained during a dynamic reconfiguration
Keywords :
fault tolerant computing; hypercube networks; network routing; parallel processing; adaptive routing; fault-tolerance; faulty k-ary n-cubes; interconnection networks; massively parallel computers; partial irregular-network routing; progressive deadlock-recovery; Computer networks; Concurrent computing; Distributed computing; Fault tolerance; Fault tolerant systems; Multiprocessor interconnection networks; Routing; System recovery; Telecommunication traffic; Throughput; Adaptive routing; fault tolerance; interconnection networks; massively parallel computers; progressive deadlock recovery;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Innovative Architecture for Future Generation High Performance Processors and Systems, 2006. IWIA '06. International Workshop on
Conference_Location :
Kohaha Coast, HI
ISSN :
1537-3223
Print_ISBN :
0-7695-2689-6
Type :
conf
DOI :
10.1109/IWIAS.2006.23
Filename :
4089356
Link To Document :
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