Statistical leakage estimation of bounds on nanometric CMOS circuits

In this work is presented one method of statistical leakage estimation of bounds in CMOS circuits based on the characterization of standard CMOS cell libraries. The leakage estimation takes in account the correlations (rho) of cells structure, input patters and variations on principal process parameters. Also it was considered the presence of Intra-Die process variations for spatial correlations beta = 1 and 0 larr beta rarr 1. For the complete ISCAS85 Benchmark under study the mu and sigma² absolute errors varies between 0.0048 to 0.1278 & 0.0301 to 0.3801 for lower bound and 0.0306 to 0.1247 & 0.0411 to 0.2016 for upper bound.