DocumentCode :
3420841
Title :
Statistical leakage estimation of bounds on nanometric CMOS circuits
Author :
Vázquez, Raymundo Mendoza
Author_Institution :
Dept. d´´Eng. Electron., Univ. Politec. de Catalunya, Barcelona
fYear :
2009
fDate :
6-9 April 2009
Firstpage :
58
Lastpage :
63
Abstract :
In this work is presented one method of statistical leakage estimation of bounds in CMOS circuits based on the characterization of standard CMOS cell libraries. The leakage estimation takes in account the correlations (rho) of cells structure, input patters and variations on principal process parameters. Also it was considered the presence of Intra-Die process variations for spatial correlations beta = 1 and 0 larr beta rarr 1. For the complete ISCAS85 Benchmark under study the mu and sigma2 absolute errors varies between 0.0048 to 0.1278 & 0.0301 to 0.3801 for lower bound and 0.0306 to 0.1247 & 0.0411 to 0.2016 for upper bound.
Keywords :
CMOS integrated circuits; leakage currents; nanoelectronics; semiconductor process modelling; ISCAS85 Benchmark; cells structure; input patters; intra-die process; nanometric CMOS circuits; principal process parameter variations; statistical leakage estimation; CMOS process; CMOS technology; Circuits; Doping profiles; Gate leakage; Leakage current; Libraries; Semiconductor device modeling; Table lookup; Upper bound; Leakage Currents; Leakage Estimation; Statistical Leakage Bounds;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-4320-8
Electronic_ISBN :
978-1-4244-4321-5
Type :
conf
DOI :
10.1109/DTIS.2009.4938024
Filename :
4938024
Link To Document :
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