DocumentCode
3421106
Title
Towards hierarchical cluster based cache coherence for large-scale network-on-chip
Author
Zhang, Yuang ; Lu, Zhonghai ; Jantsch, Axel ; Li, Li ; Gao, Minglun
Author_Institution
Key Lab. of Adv. Photonic & Electron. Mater., Nanjing Univ., Nanjing
fYear
2009
fDate
6-9 April 2009
Firstpage
119
Lastpage
122
Abstract
We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.
Keywords
cache storage; distributed memory systems; large scale integration; network-on-chip; cache coherence scheme; communication cost; distributed memory architectures; large-scale network-on-chip; memory overhead; Bandwidth; Delay; Large-scale systems; Network-on-a-chip; Protocols; Scalability; Space exploration; System performance; Telecommunication traffic; Very large scale integration; Cache coherence; Hierarchical directory; Network cluster; Network-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on
Conference_Location
Cairo
Print_ISBN
978-1-4244-4320-8
Electronic_ISBN
978-1-4244-4321-5
Type
conf
DOI
10.1109/DTIS.2009.4938037
Filename
4938037
Link To Document