Quantum transport based simulation and design optimization of a 10 nm FinFET

The International Technology Roadmap for Semiconductors (ITRS) projected value for the High Performance (HP) MOSFET channel length is 10 nm at the year 2016. The FinFET is expected to replace the conventional bulk MOSFET beyond the 22 nm node due to the latter´s scaling challenges. In this article the design optimization of a 10 nm FinFET is considered. It is shown that the ITRS requirements for the FinFET´s driving current and switching speed can be satisfied simultaneously. The on-current and switching speed can be as large as 6734 muA/mum and 24.4 THz compared to the 4590 muA/mum and 5.6 THz of the ITRS projections. It is also shown that the use of a mid-gap work function can satisfy the ITRS requirements. Moreover, factors for better manufacturability like relaxed extension lateral abruptness and increased fin thickness are also considered in the design.