Combined scheduling and instruction selection for processors with reconfigurable cell fabric

This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.