240 MPOS reconfigurable parallel VLSI processor for robot control

A computationally efficient algorithm called a subsequent-division algorithm is presented to develop a special-purpose VLSI processor for differential inverse kinematics computation of redundant manipulators. Because the computation is performed in a feedback loop not only the throughput but also the delay time must be considered as a performance factor. An architecture of a reconfigurable parallel VLSI processor is proposed to reduce the delay time by improvement of the ratio of the multipliers contained in the processing elements (PEs). Chip evaluation based on the 1-μm CMOS design rule shows that the delay time for differential inverse kinematics (DIK) computation of a 12-degree-of-freedom (DOF) redundant manipulator becomes about 13 μm, which is about 90 times faster than that of a parallel processor approach using general-purpose microprocessors