A low-power high-precision tunable WINNER-TAKE-ALL network

Author

Canegallo ; Chinosi ; Kramer

Author_Institution

Neural Network Design Group, SGS-Thomson Microelectron., Agrate Brianza, Italy

fYear

1996

fDate

12-14 Feb 1996

Firstpage

292

Lastpage

296

Abstract

This paper describes a low power CMOS circuit for selecting the greatest of n analog voltages within a tunable selection range. An increasing speed-decreasing precision law is used to determine the amplitude of the selection range. 16 mV to 4 mV resolution, over a 2 V to 4 V dynamic input range, can be obtained by reducing the speed from 2 MHz to 500 kHz. 1 μA quiescent current, 2 μA AC current for the selected cells and small size make this circuit available for VLSI implementations of massively parallel analog computational circuits

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; neural chips; parallel processing; 1 muA; 2 muA; 2 to 4 V; 4 to 16 mV; 500 kHz to 2 MHz; VLSI implementation; WTA circuit; analog computational circuits; high-precision operation; low-power CMOS circuit; massively parallel computational circuits; tunable network; winner-take-all network; Analog computers; CMOS technology; Capacitors; Circuit testing; Computer architecture; Computer networks; Concurrent computing; Threshold voltage; Tunable circuits and devices; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural Networks, 1996., Proceedings of Fifth International Conference on

Conference_Location

Lausanne

ISSN

1086-1947

Print_ISBN

0-8186-7373-7

Type

conf

DOI

10.1109/MNNFS.1996.493805

Filename

493805